? semiconductor components industries, llc, 2001 december, 2000 rev. 3 1 publication order number: cs3524a/d cs3524a voltage mode pwm control circuit with 200 ma output drivers the cs3524a pwm control circuit retains the same versatile architecture of the industry standard cs3524 (sg3524) while adding substantial improvements. the cs3524 is pincompatible with anonao versions, and in most applications can be directly interchanged. the cs3524a, however, eliminates many of the design restrictions which had previously required additional external circuitry. the cs3524a includes a precision 5.0 v reference trimmed to 1% accuracy (eliminating the need for potentiometer adjustments), an error amplifier with an output voltage swing extending to 5.0 v, and a current sense amplifier useful in either the ground or power supply output lines. the uncommitted 60 v, 200 ma npn output pair greatly enhances the output drive capability. the cs3524a features an undervoltage lockout circuit which disables all internal circuitry (except the reference) until the input voltage has risen to 8.0 v. this holds standby current low until turnon, and greatly simplifies the design of low power, offline supplies. the turnon circuit has approximately 600 mv of hysteresis for jitter free activation. other improvements include a pwm latch that insures freedom from multiple pulsing within a period, even in noisy environments; logic to eliminate double pulsing on a single output, a 200 ns external shutdown capability, and automatic thermal protection from excessive chip temperature. the oscillator circuit is usable to 500 khz and is easier to synchronize with an external clock pulse. features ? precision reference internally trimmed to 1% ? current limit ? undervoltage lockout ? startup supply current < 4.0 ma ? output to 200 ma ? 60 v output capability ? wide commonmode input range for error and current limit amplifiers ? pwm latch insures single pulse per period ? double pulse suppression ? 200 ns shutdown ? guaranteed frequency ? thermal shutdown http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week so16l dw suffix case 751g 1 16 device package shipping ordering information cs3524agn16 dip16 25 units/rail cs3524agdw16 so16l 46 units/rail cs3524agdwr16 so16l 1000 tape & reel dip16 n suffix case 648 1 16 marking diagrams 16 1 cs3524a awlyyww pin connections v outb i sense+ e b sync v in ea+ v ref ea 1 comp gnd shutdown c t e a r t v outa i sense 1 cs3524a awlyyww 16
cs3524a http://onsemi.com 2 figure 1. block diagram v ref v outa e a v outb e b shutdown gnd v in sync r t c t comp ea ea+ i sense+ i sense osc 5 v reference regulator uv sense ramp clock comp + + ea cl pwm latch flip flop power to internal circuitry t r s s v in v in 200 mv 1 k w 10 k w absolute maximum ratings* rating value unit supply voltage (v in ) 40 v collector supply voltage (v cc ) 60 v output current (each output) 200 ma reference output current 50 ma oscillator charging current 5.0 ma power dissipation at t a = 25 c 1000 mw power dissipation at t j = +25 c derate for case temperature above +25 c 2000 16 mw mw/ c storage temperature range 65 to +150 c lead temperature soldering wave solder (through hole styles only) note 1. reflow (smd styles only) note 2. 260 peak 230 peak c c 1. 10 seconds max. 2. 60 seconds max above 183 c *the maximum package power dissipation must be observed.
cs3524a http://onsemi.com 3 electrical characteristics (0 c t a +70 c, v in = v cc = 20 v; unless otherwise specified.) characteristic test conditions min typ max unit turnon characteristics input voltage operating range after turnon 8.0 40 v turnon threshold 5.5 7.5 8.5 v turnon current v in turnon 100 mv 2.5 4.0 ma operating current v in = 8.0 to 40 v 5.0 10 ma turnon hysteresis (note 3.) 0.6 v reference section output voltage t a = 25 c 4.9 5.0 5.2 v line regulation v in = 10 to 40 v 10 30 mv load regulation i l = 0 to 20 ma 20 50 ma temperature stability (note 3.) over operating range 20 50 mv short circuit current v ref = 0, t a = 25 c 80 100 ma output noise voltage (note 3.) 10 hz f 10 khz, t a = 25 c 40 m v rms long term stability (note 3.) t a = 125 c, 1000 hrs. 20 50 mv oscillator section r t = 2700 , c t = 0.01 f; unless otherwise specified initial accuracy t a = 25 c 39 43 47 khz temperature stability (note 3.) over operating temperature range 1.0 2.0 % minimum frequency r t = 150 k w , c t = 0.1 m f 120 hz maximum frequency r t = 2.0 k w , c t = 470 pf 500 khz output amplitude (note 3.) t a = 25 c 3.5 v output pulse width (note 3.) t a = 25 c 0.5 m s ramp peak 3.3 3.5 3.7 v ramp valley 0.7 0.9 1.0 v error amplifier section v cm = 2.5 v; unless otherwise specified input offset voltage 2.0 10 mv input bias current 1.0 10 m a input offset current 0.5 1.0 m a common mode rejection ratio v cm = 1.5 to 5.5 v 60 75 db power supply rejection ratio v in = 10 to 40 v 50 60 db output swing minimum total range 0.5 5.0 v open loop voltage gain d v out = 1.0 to 4.0 v, r l 10 m w 60 80 db gainbandwidth (note 3.) t a = 25 c, a v = 0 db 3.0 mhz current limit amplifier v sense = v o ; unless otherwise specified input offset voltage t a = 25 c, ea set for max. output 180 200 220 mv input offset voltage over operating temperature range 170 230 mv input bias current 1.0 10 m a common mode rejection ratio v sense = 0 to 15 v 50 60 db power supply rejection ratio v in = 10 to 40 v 50 60 db 3. these parameters are guaranteed by design but not 100% tested in production.
cs3524a http://onsemi.com 4 electrical characteristics (continued) (0 c t a +70 c, v in = v cc = 20 v; unless otherwise specified.) characteristic unit max typ min test conditions current limit amplifier (continued) v sense = v o ; unless otherwise specified output swing minimum total range 0.5 5.0 v open loop voltage gain d v out = 1.0 to 4.0 v, r l 10 m w 70 80 db delay time (note 4.) d v in = 300 mv 300 ns output section (each output) collector emitter voltage i c = 100 m a 60 80 v collector leakage current v ce = 50 v 0.1 20 m a saturation i c = 20 ma i c = 200 ma 0.2 1.0 0.4 2.2 v v emitter output voltage i e = 50 ma 17 18 v rise time (note 4.) t a = 25 c, r = 2.0 k w 200 ns fall time (note 4.) t a = 25 c, r = 2.0 k w 100 ns comparator delay (note 4.) t a = 25 c, v comp to v out 300 ns shutdown delay (note 4.) t a = 25 c, v shut to v out 200 ns shutdown threshold t a = 25 c, r c = 2.0 k w 0.5 0.7 1.0 v thermal shutdown (note 4.) 165 c 4. these parameters are guaranteed by design but not 100% tested in production. typical performance characteristics figure 2. error amplifier voltage gain vs. frequency over rf figure 3. duty cycle vs. input voltage 100 1 k 10 k 100 k 1 m frequency (hz) 80 60 40 20 0 open voltage gain (db) r f = r f = 1 m w r f = 300 k w r f = 100 k w r f = 30 k w v in = 20 v t a = 25 c r f is impedance to ground. values below 30 k w will begin to limit the maximum dutycycle. 0123 5 input voltage v in 50 40 30 0 dutycycle (one output) % 10 20 4 v in = 20 v r t = 2700 w t a = 25 c c t = 10 m f c t = 1 m f
cs3524a http://onsemi.com 5 figure 4. quiescent supply current vs. supply voltage over temperature figure 5. shutdown delay from pwm comparator 10 20 30 40 50 supply voltage v in (v) 9 7 5 3 1 quiescent current (ma) 10 8 6 4 2 0 0 t a = 55 c t a = 25 c t a = 125 c note: outputs off. r t = 0 123 delay time ( m s) 20 input (v) 15 10 5 0 5 4 3 2 1 0 output (v) v in = 20 v r l = 2 k w t a = 25 c note: minimum input pulse width to latch is 200 ns. output at v oa or v ob input at v ob figure 6. oscillator frequency vs. timing components resistor over timing capacitance 1 m 100 k 10 k 100 oscillator frequency (hz) 1 k 1 2 5 20 100 timing resistor, r t (k w ) 50 10 v in = 20 v t a = 25 c f 1.15 r t c t 1. c t = 1.0 nf 2. c t = 3.0 nf 3. c t = 10 nf 4. c t = 30 nf 5. c t = 100 nf 1 2 3 4 5 12 5 20 100 timing capacitor, c t (nf) 50 10 10 5.0 0.1 output dead time ( m s) 2.0 1.0 0.5 0.2 v in = 20 v r t = 2700 w t a = 25 c note: dead time = osc output pulse width plus output delay figure 7. output dead time vs. timing capacitor value 12 4 delay time ( m s) input (v) output (v) 5 6 4 3 2 1 0 0.2 0.1 0 3 0 output at comp overdrive 5% 10% 20% 50% input at i sense+ v in = 20 v, t a = 25 c ea+ = v ref i sense = gnd 01 23 delay time ( m s) note: minimum input pulse width to latch is 200 ns. input (v) output (v) 5 10 0 1.0 0.5 0 15 20 v in = 20 v r l = 2.0 k w t a = 25 c output at v oa or v ob input at shutdown figure 8. current limit amplifier delay figure 9. turnoff delay from shutdown
cs3524a http://onsemi.com 6 0 50 100 150 output collector current (ma) v ce sat (v) 5 3 2 1 0 4 200 250 t a = 125 c t a = 25 c t a = 55 c figure 10. output saturation voltage vs. output current over temperature figure 11. open loop test circuit v ref v outa e a v outb e b shutdown gnd v in sync r t c t comp ea ea+ i sense+ i sense cs3524a v cc 2 k w 1 w 2 k w 1 w 2 k w shutdown r t c t 0.1 i s 100 k w 100 k w 10 k w 1 k w 2 k w 0.1 10 k w note: the cs3524a should be able to be tested in any 3524 test circuit with two possible exceptions: 1. the higher gainbandwidth of the current limit amplifier in the cs3524a may cause oscillations in an uncompensated 3524 test circuit. 2. the effect of the shutdown cannot be seen at the compensation terminal, but must be observed at the outputs.
cs3524a http://onsemi.com 7 package dimensions dip16 n suffix case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 so16l dw suffix case 751g03 issue b d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 package thermal data parameter dip16 so16l unit r q jc typical 42 23 c/w r q ja typical 80 105 c/w
cs3524a http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs3524a/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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